Data transmitted across a high-speed system, such as between two chips on a highly, integrated system or between circuits within a single chip, are typically sent without an accompanying clock signal. Although clock-less data transmission reduces complexity and power consumption, the receiver of the data is required to generate a clock signal to recover the data. The receiver may employ a clock and data recovery (CDR) circuit to generate a clock signal in synchronization with the phase and frequency of the received data. Accurate detection of the phase and frequency of the received data or the phase and frequency offsets between the clock signal and the data signal is therefore important to ensure high quality data communication, especially for high-speed data systems that operate at about 10 gigabits per second (Gbps) to about 100 Gbps.